The demonstration of Broadcom and a follow -up session explored the advantages of CPC development, such as a reduction in signal integrity penalties and an extensive scope, by modeling and channel simulations, wrote Broadcom in a blush About the Designcon event.
“The experimental results have shown a successful implementation of CPC, demonstrating its potential to meet the bandwidth and the challenges of signal integrity in data centers, which is crucial for AI applications,” said Broadcom.
In addition to the demo, Broadcom and Samtec have also written a white paper on CPC which indicated: “Co-Emballée connectivity (CPC) offers the possibility of omitting the loss and reflection penalties of the [printed circuit board (PCB)] and the package. When high -speed E / S are wired at the top of the package, advanced PCB materials are not necessary. The losses from vertical package paths and routing of PCBs can be transferred at the longer range of cables, “said the authors.
“As very complex systems are challenged to scale the number of E / O and their scope, the co-Emballée connectivity has an opportunity. Approaching 224G-PAM4 [which uses optical techniques to support 224 Gigabits per second data rates per optical lane] And above, the loss of system and dominant noise sources require the need to reconstruct what has been limited to the rear of the system of the system for years: what if we attach to the packaging? »»
At OFC, Samtec has demonstrated its sets of Si-Flyhd Co-Emballées and Samtec Flyoveroctal Small Factor Pluggable (OSFP) on the Copper Copper Copper at Hyper-Favory Speed of Samtec Speed Hyper Low. Overview Samtec’s owner, addresses the integrity of the signal and the limits for the realization of high -speed signals via traditional printed circuits (PCB).
“”This evaluation platform incorporates the 200G technology technology from Broadcom and Samtec Co-Emballé overflight technology. Si-Fly HD CPC offers the highest density of footprint and a robust interconnection of the industry which allows 102.4 t (512 lanes to 200g) in a chip substrate 95 x 95 mm ”, Samtec wrote.
